library verilog;
use verilog.vl_types.all;
entity piano_top_vlg_check_tst is
    port(
        code1           : in     vl_logic_vector(6 downto 0);
        high1           : in     vl_logic;
        spkout          : in     vl_logic;
        sampler_rx      : in     vl_logic
    );
end piano_top_vlg_check_tst;
